FIG. 1A illustrates a conventional magnetic tunnel junction (MTJ) device 100. The MTJ 100 is typically comprised of a stack of two ferromagnetic layers (ML) separated by a tunnel barrier (TL) at a cross-point of two conductors, one of which may be a word line (WL) and the other a bit line (BL). One of the two magnetic layers is often referred to as a free magnetic layer. The magnetic orientation of the free magnetic layer can be changed by the superposition of magnetic fields generated by programming currents IWL and IBL flowing in the conductors WL and BL, respectively. The other of the two magnetic layers ML is often referred to as a fixed magnetic layer. The programming currents IWL and IBL cannot change the magnetic orientation of the fixed magnetic layer. The logical state (e.g., a “0” bit or a “1” bit) is stored in the MTJ 100 by changing the orientation of the free magnetic layer relative to the fixed magnetic layer. When both magnetic layers have the same orientation 102, the MTJ 100 typically has a low resistance Rc associated therewith, as measured between conductors WL and BL, and in this case Rc is more specifically referred to as Rparallel. Likewise, the resistance Rc of the MTJ 100 is generally high when the magnetic layers are oriented in opposite directions 104 with respect to one another, and in this case Rc is more specifically referred to as Rantiparallel.
A single bit of information may be selectively written into an MTJ memory cell embedded within a two-dimensional array of such cells by applying coincident and orthogonal magnetic fields within the plane of the MTJ. In conventional MTJ MRAM, the programming currents IWL and IBL generate a hard axis field and an easy axis field, respectively, that the change the magnetic orientation of the free magnetic layer, ML (free). The current IBL generates the easy axis field that partially selects the MTJ memory cell to be written. Of equal significance, the sign of IBL sets the state of the selected MTJ memory cell. Hence, the write current flowing through the bit line BL, namely, IBL, must flow conditionally in one of two directions, and will be referred to henceforth as a bidirectional write current. The current IWL generates the hard axis field that partially selects the MTJ memory cell to be written. In contrast to IBL, the write current flowing through the word line WL, namely, IWL, need only flow in one direction and will be referred to henceforth as a write select current.
A conventional MRAM generally includes a plurality of MTJ devices connected in an array configuration. FIG. 1B illustrates a conventional cross-point memory array, wherein each memory cell comprises a single MTJ device coupled at an intersection of a word line (e.g., WLk−1, WLk, WLk+1) and a corresponding bit line (e.g., BLi−, BLi, BLi+1). MRAM circuits are discussed in further detail, for example, in the article by W. Reohr et al., entitled “Memories of Tomorrow,” IEEE Circuits and Devices Mag., pp. 17–27, Vol. 18, No. 5, Sep. 2002, which is incorporated herein by reference.
Generally, within the cross-point memory array, the write select current is required to aid in the selection of one or more memory cells in the array. One or more bidirectional write currents, corresponding to one or more respective memory cells of a one or more bit word, are required for writing the selected memory cells to a zero or one logical state. Word lines and bit lines routed throughout the memory array convey the programming current and sense current for writing and reading, respectively, selected memory cells in the array.
In a conventional cross-point MRAM device, during a read operation, the bit lines convey the sense current between a sense amplifier and the memory cell to read the state of the memory cell. During a write operation, the bit lines convey the bidirectional write current in close proximity to the MTJ device of the selected memory cell to write the selected memory cell, while a word line simultaneously conveys the write select current in close proximity to the aforementioned MTJ device to write the selected memory cell.
Since the sense current is substantially smaller in magnitude than either of the programming currents (e.g., about 50 microamperes versus about 5 milliamperes, respectively), the sense current is considerably more sensitive to noise. Additionally, the read access time of the memory array depends, to a large extent, on reliably extracting the state of the memory cell from this relatively small sense current. Consequently, the number of memory cells that can be placed along a given bit line should be limited to minimize the read access time of the memory array.
Since the supply voltage applied to modern memory devices is typically constrained to below three volts and the sheet resistance of metal interconnects is typically close to about 0.1 ohm, the large programming currents required in the memory array limit the number of memory cells that can be placed along the bit line or word line dimensions. Therefore, reducing the number of memory cells along a bit line dimension to increase read access time, as previously stated, without also increasing the number of memory cells along a word line dimension would undesirably reduce the array efficiency, which can be defined as a percentage of the total semiconductor area devoted to the memory cells.
There exists a need, therefore, for an improved MRAM circuit which provides an increased read access time without significantly reducing the array efficiency of the MRAM device. Furthermore, it would be desirable to provide an improved 1T1MTJ (one transistor/one MTJ) MRAM circuit that enables a smaller memory cell size to be realized.